International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC) 2022

Conference Proceedings

The International Conference on Emerging Technologies in Electronics, Computing and Communication 2022


Multirate FIR Filter Using Radix Sort Booth Algorithm In Xilinx System Generator

Zulfiqar Ali1; Syed Tahir Hussain Shah1; Muhammad Ayaz1*; Sania Syed1; Wesam Khalil2;
1Department of Electronics Engineering University of Engineering & Technology Peshawar, Abbottabad Campus
2Intel Corporation, 2111 NE 25Th Ave Hillsboro, USA

Multirate FIR filters are extensively used in digital signal processing in which different filter parts operate at different rates. It has applications in communication transmitters and receivers, and Up-sampling, which is increasing of the samples of frequency, before Digital/Analog conversion in order to meet the requirements of the analog low-pass antialiasing filter. The process of interpolation consists of two steps. In multirate signal processing interpolation and decimation are performed in two steps: In first step samples are increased in case of interpolation and decreased in decimation. In second step the low pass filter assigns required values to the zero values in the samples or in frequency domain it rejects the imaging frequencies created by the up-sampling process and down-sampling process. Multirate FIR filters when implemented use multipliers and accumulators. There are many different types of multipliers such as Combinational multiplier, Wallace Tree multiplier, Array multiplier and Sequential multiplier and Booth multiplier. Booth multipliers reduces the total number of partial products generated as a result of multiplication of two binary numbers. Mutlirate FIR filter has been implemented using with radix-2, 4, 8, 16 and 32 booth recoding algorithm. The multirate 23-tap FIR filter has been implemented using Xilinx System Generator 14.7 which is compatible with MATLAB 2013b. Booth multipliers using different radix sort has been done using Verilog in Xilinx 14.7 and then the synthesized code is imported to Xilinx system generator (MATLAB). The concept of booth multipliers has been incorporated and that results in area efficient and reducing the delay offered by the multipliers and thereby enhancing the speed and power dissipation as compared to general signed multiplier